1. Field of the Invention
Embodiments of the present invention facilitate reducing power consumption in integrated circuits. More specifically, embodiments of the present invention facilitate automatically generating circuitry to provide clock-gating for clocked memory elements in an integrated circuit, wherein the clock-gating circuitry reduces switching and thereby saves power in the integrated circuitry.
2. Related Art
Advances in semiconductor manufacturing technologies have led to significant increases in microprocessor performance. Unfortunately, as microprocessor clock speeds continue to increase, there has been a corresponding increase in the amount of power consumed by the microprocessor. This increase in power consumption increases the amount of heat produced by the microprocessor. As a consequence, energy efficiency is becoming an increasingly important consideration in the design of high-end microprocessor systems.
Dynamic or “switching” power is one type of power which is consumed when circuits switch state in a digital system. This switching power can account for as much as 30% of total power consumption in an integrated circuit. To reduce switching power, some microprocessor designers have implemented “clock-gating” techniques in microprocessor systems. Clock-gating is implemented by adding logic to selectively disable (i.e., turn off) clock signals for some sequential memory elements. During clock-gating, circuitry can be added to disable a clock for a sequential element when the element does not change state. Because sequential elements retain their output values when the clock is not switching, the clock can be disabled without affecting the operation of the circuit.
Clock-gating can significantly reduce switching power in a microprocessor. This reduction in switching power can cause a corresponding reduction in the temperature of the microprocessor. Moreover, because sub-threshold leakage currents can vary exponentially with temperature, clock-gating can lead to a significant reduction in leakage currents, which can, in turn, reduce leakage power.
Clock-gating can be implemented by manually identifying clock-gating opportunities. However, this manual process is tedious and time-consuming, which can limit the manual approach to only a small subset of the sequential elements in the microprocessor circuit. In practice, it is desirable to implement clock-gating with automated tools that can identify clock-gating opportunities and can insert clock-gating logic.
Unfortunately, automated tools fail to identify some clock-gating opportunities. For example, some automated tools operate on a high-level model for the microprocessor (e.g., RTL model) and can fail to identify clock-gating opportunities in the final gate-level netlist. Also, because mapping and logic optimization is performed before clock-gate insertion, automated tools can overlook clock-gating opportunities when enable conditions for some sequential elements change (e.g., as a result of buffering or other optimizations).
Hence, what is a needed is a technique for automatically inserting clock-gating logic into a circuit without the above-described problems.